1. Technical Field
The present invention relates generally to a notched compound semiconductor wafer. More specifically, the invention relates to a notched compound semiconductor wafer having a plane orientation which is tilted in a predetermined direction from the orientation of a crystal plane of a compound semiconductor crystal.
2. Background Art
As semiconductor wafers (which will be hereinafter referred to as “wafers”), such as Si, GaAs and InP wafers, circular wafers are widely used. As a crystal plane for forming a device, a crystal plane about a predetermined plane orientation, such as a (100), (111) or (511) plane, is usually used. In particular, a wafer having a plane orientation coming very close to the (100) plane is important.
The ion-implantation or epitaxial growth method is used for forming a device on the surface of a wafer of GaAs or InP being a typical compound semiconductor. As a wafer used for ion-implantation, there is usually used a wafer having a plane orientation which has a tolerance of 0.5° or less from the (100) plane. On the other hand, as a wafer used for epitaxial growth, there is often used a wafer having a crystal plane which is intentionally tilted from the (100) plane in a predetermined crystal orientation, since the smoothness of the formed surface of the wafer is important. That is, since there is no atomic step on the just (100) plane in theory, flying material atoms can not find any step edges within a diffusion distance (diffusion length) on the surface, so that it is difficult to smoothly carry out growth. However, if an atomic step is formed by intentionally shifting the plane orientation of the wafer from the (100) plane, material atoms fall in the step within the diffusion length, so that there are some cases where good epitaxial growth can be carried out.
FIG. 1 schematically shows the directions of bonds of atoms on the (100) uppermost surface of a compound semiconductor of GaAs as an example of a binary compound semiconductor having a zincblende crystal structure. As shown in this figure, the dangling bonds on the atomic plane of Ga extend in front and rear directions on the figure, and the dangling bonds on the atomic plane of As extend in right and left directions on the figure. In addition, the directions of the bonds of Ga atoms are parallel to a [0−1−1] direction, and the directions of the bonds of As atoms are perpendicular to the [0−1−1] direction. Therefore, the [0−1−1] direction shown in FIG. 1 has different properties from those of a [01−1] direction shown in FIG. 1. Furthermore, throughout the specification, it is assumed that a negative directional index is expressed by giving the sign “−” before a number although it is generally expressed by giving a bar above a number. Similarly, it is assumed that a coordinate of a lattice plane is expressed by giving the sign “−” before a number when it is negative.
As shown in FIG. 2, if crystal growth proceeds on a step edge, the directions of bonds on the step edge influence on the crystal growth, so that a direction in which the plane orientation of a wafer is to be tilted is very important. Therefore, a direction (which will be hereinafter referred to as an “off direction”), in which the plane orientation of a wafer to be sliced is tilted, defines a crystallographic orientation as a specification of the wafer.
In order to clarify a crystallographic orientation on a plane of a wafer, an orientation flat or notch is generally formed in the outer peripheral portion of the wafer. FIG. 3 shows an atomic arrangement of GaAs when a semiconductor wafer of GaAs having a crystal plane of (100) plane is viewed from the (0−1−1) side assuming that the surface of the wafer is arranged in a [100] direction. From this figure, it can be seen that the directions of the bonds of atoms on the surface of the wafer are different from those on the reverse thereof by 90°. Therefore, a typical compound semiconductor wafer has a secondary flat in addition to a primary orientation flat in order to prevent the surface and reverse thereof from being erroneously recognize.
In the case of an Si wafer formed of simple atoms, even if the surface of the wafer is mistaken for the reverse thereof before working, there is no problem since it has no anisotropy. In addition, there is little possibility that the surface of the wafer may be mistaken for the reverse thereof since only the device forming surface is mirror-finished. On the other hand, in the case of a compound semiconductor wafer, it is more difficult to work the compound semiconductor wafer than the case of the Si wafer, and the strength of the compound semiconductor wafer is weaker than that of the Si wafer. Therefore, if the compound semiconductor wafer has a diameter of four inches or more, both sides thereof are generally mirror-finished in order to meet the demands for higher working precision and strength.
In such circumstances, the position of an orientation flat to be formed in a compound semiconductor wafer having a diameter of four inches or less is standardized. An example of such a standard is SEMI standard 9−0999. As shown in FIGS. 4A and 4B, this standard includes a so-called US (American) type standard (FIG. 4A) wherein a primary orientation flat is arranged on the (01−1) plane and a secondary orientation flat is arranged on the (011) plane, and a so-called EJ (Euro-Japanese) type standard (FIG. 4B) wherein a primary orientation flat is arranged on the (0−1−1) plane and a secondary orientation flat is arranged on the (0−11) plane.
In the case of a so-called just wafer which is sliced without being tilted from the (100) plane, it is sufficient just to conversely work the surface and reverse of the wafer, so that it is sufficient just to keep only one kind of sliced wafers as semi-finished products in stock before mirror finish.
However, in the case of a wafer which is sliced so as to be tilted from the (100) plane in a predetermined direction, there is a problem in that the crystallographic orientation in the off direction varies if the wafer is turned over. For example, when a wafer having EJ type orientation flats is sliced so as to be tilted in a [0−1−1] direction in which a primary orientation flat is arranged, i.e., toward the (111) A plane, if the wafer is mistaken for a wafer having US type orientation flats to work the reverse thereof, it is tilted toward the (111) B plane with respect to the primary orientation flat. Referring to FIGS. 5A and 5B, this will be described below. FIGS. 5A and 5B show the relationship between the shape of an etch pit on the (100) plane of GaAs due to molten KOH etching and the crystal orientation. As can be seen from these figures, if the wafer is turned over, the direction of the etch pit is shifted by 90° with respect to the primary orientation flat, i.e. the crystallographic orientation is shifted by 90°, and the position of the secondary orientation flat is reversed right and left, so that the wafer becomes an absolutely different wafer. Therefore, it is not possible to cope with the wafer as a just wafer.
Only in a case where the wafer is sliced so as to be tilted in an intermediate direction between the (111) A plane and the (111) B plane, it is possible to obtain a crystallographically equivalent direction. However, there is a problem in that the relative off direction with respect to the orientation flat is different as shown in FIGS. 6A and 6B.
With respect to a wafer having a diameter of six inches, it was attempted to determine the position of a primary (secondary) orientation flat to define the length of a substantially similar figure, on the extended line of details of a wafer having a diameter of four inches or less. However, since the length of the primary orientation is too long, (1) the balance of the wafer in its rotation during a process is bad, (2) the temperature distribution in the wafer during a heating process is easy to be bad, and (3) the yield of a device deteriorates. In such circumstances, it is standardized by SEMI standard M9.7-0200 that a notch is provided at a place of the wafer as shown in FIGS. 7A and 7B. In this standard, it is standardized that a notch is provided at a position in a [010] direction, not at the crystallographic position of an orientation flat as a conventional notch. That is, since the notch is provided at a position in an intermediate direction between the (111) A plane and the (111) B plane as shown in FIGS. 7A and 7B, the crystallographic orientations of the notch in front and rear directions and in right and left directions are not changed even if the wafer is turned over in the case of the just (100) wafer. This standard has the merits of the fact that it is not required to identify and manage the surface and reverse of a wafer in a working process from a slicing step to a step of polishing a mirror-finished surface for forming a device thereon.
However, the above described prior art does not consider the management of the surface and reverse of a wafer sliced so as to be tilted from the (100) plane, although it can greatly lighten the load on the management of the surface and reverse of the just (100) wafer. That is, in Table 1 and FIG. 3 of SEMI standard M9.7-0200, it is standardized that a wafer is sliced so as to be tilted in a [010] direction, in which a notch is to be formed, when the wafer is sliced so as to be tilted in a direction of a group of <110> directions. In this case, as shown in FIGS. 8A and 8B, if the wafer is turned over, the off direction is the opposite direction to the direction of a notch by 180°. That is, the wafer has a different specification if the surface of the wafer is mistaken for the reverse thereof.
As described above, since both sides of a wafer having a diameter of six inches are mirror-polished, it is not easy to identify the surface and reverse of the wafer with the naked eye. Therefore, it is required to take measures to identify the surface and reverse of the wafer during a process for working the wafer, and to manage the wafer so that the wafer is not turned over. In order to take such measures, a laser marking is provided on one side of the wafer at the initial stage of the wafer working process. However, since the laser marking disappears during the polishing of the wafer unless its depth is greater than a margin for the subsequent working, it is required to deeply dig the laser marking. However, since the wafer has a thickness tolerance (usually ±10 to 20 μm), even if the laser marking is so deeply dug, there are problems in that it is difficult to see a portion for indicating a wafer lot by the laser marking and that the deeply remaining laser marking causes to damage the wafer.
As another method, there is known a method for asymmetrically chamfering the outer peripheral portions of a wafer so that the amount of chamber on the side of the surface thereof is different from that on the side of the reverse thereof, and for observing the side of the wafer to identify the surface and reverse of the wafer (see Japanese Patent Laid-Open No. 8-195366). However, this method is not always accepted by all customers since it is easy to depart from the standard shown in FIG. 7 and Table of SEMI standard M9-0999.
As a further method, there is provided a method for identifying the surface and reverse of a wafer by asymmetrically chamfering the outer peripheral portions of the wafer so that the amount of chamfer of only a notch portion on the side of the surface thereof is different from that on the side of the reverse thereof while satisfying the standard of the shape of chamber in the outer peripheral portions (see Japanese Patent Laid-Open No. 2000-331898). This method is promising as a solution. However, since the notch portion is a portion which engages an aligning pin, the slight trouble is that the rate of breakage of wafers increases in the case of a compound semiconductor, such as GaAs or InP, which is easily broken.